The present invention relates generally to integrated circuits and, more specifically, to debugging integrated circuits.
Integrated circuits are an integral part of the modem world. Presently, integrated circuits are becoming increasingly complex as advances in technology and functionality are continually developed. An important consideration in the design of integrated circuits is the ability to quickly and accurately debug them. Debugging involves attempting to find and correct software and hardware errors present in the integrated circuit to prevent failures and improve reliability. Accordingly, there is a need for integrated circuits which can be quickly and accurately debugged.
Currently, external digital analyzers are widely used by external test equipment to debug integrated circuits. External digital analyzers operate by monitoring the external output pins of the integrated circuit. Through the external digital analyzer, the external test equipment analyzes the states of the external output pins responsive to certain signals placed on the external input pins to determine if an error has occurred within the integrated circuit. In response to the detection of an internal error, the external test equipment can attempt to resolve the errors by passing instructions and data to the integrated circuit through the external input pins, or indicate that a non-recoverable error has occurred. Since digital analyzers are capable of accessing the integrated circuit only through the external pins, internal conditions of interest for debugging, such as writeable memory content and internal node states, cannot be monitored directly. Since internal conditions cannot be monitored directly, they are monitored indirectly at the external pins. However, some internal chip states may not be accessible even though indirect monitoring. In addition, indirect monitoring can lead to false error detection because external pin conditions for an internal bug may be the same as external pin conditions for normal operation. Also, indirect monitoring can lead to inaccurate diagnoses of bugs, because an error detected at an external pin can be caused at any number of internal components in the appropriate signal path to the external pin. Therefore, without direct access to the internal inputs and outputs of these components, it may be impossible to accurately determine the precise source of a bug.
In addition, because the internal chip states must be accessed indirectly through the external chip pins, the speed at which the digital analyzer can perform debugging is limited. Debugging speed is decreased due to the fact that it may require multiple clock cycles to transfer data from the external digital analyzer to points within the integrated circuit and to thereafter transfer an internal chip state to an external output pin.
Another known method for debugging involves interfacing an external debugger with an internal architecture located within an integrated circuit. The internal architecture consists of a series of cells located at desired monitoring points within the integrated circuit. The series of cells are situated within data paths in the integrated circuit and form a shift-register. The shift-register is accessed by the external debugger through an external interface, such as an IEEE 1149.1 (JTAG) compliant interface, to perform debugging. During normal operation, data passes through the cells without interrupting the flow of data through the data paths. However, during debugging, the data paths are cut off and data can be either shifted in or out of the cells comprising the shift-register. After debugging is completed, the data paths are restored. This configuration allows data to be read from and written to internal points within the integrated circuit during debugging. However, the operation of the integrated circuit is disrupted as the cells cut off the flow of data through the data paths for a number of clock cycles as data is shifted in and out of the shift-register. This disruption prevents the integrated circuit from resuming processing where it left off prior to debugging since data and instructions which were presented at the cells during debugging are lost. An example of an internal architecture and JTAG interface can be found in U.S. Pat. No. 5,935,266 to Thurnhofer et al., titled Method for Powering-up a Microprocessor Under Debugger Control, which is incorporated herein by reference.
Since, during debugging, the shift-register cuts off the flow of data through the cells and requires a number of clock cycles to shift the data in and out of the shift register, significant delays are associated with debugging in this manner. In addition, because the integrated circuit accesses the internal points serially through a shift register, internal conditions of interest for debugging, such as writeable memory content and internal node states, cannot be monitored during normal operation of the integrated circuit. This prevents debugging from occurring in real-time, thereby making real-time bugs difficult, if not impossible, to diagnose. Monitoring the integrated circuit through the use of a shift-register also leads to slow debugging speeds which result from the number of clock cycles necessary to shift desired information into and out of the shift registers. Due to the complexity of integrated circuits, it is difficult and time consuming to accurately monitor and represent the internal states of the integrated circuit through the limited number of cell connections of the shift register. In addition, it is difficult and time consuming to insert data and instructions into the integrated circuit for debugging.
FIG. 2 depicts an integrated circuit having an internal architecture with a JTAG interface for interfacing with an external debugger, as described in the preceding paragraphs. The internal architecture facilitates debugging. In FIG. 2, the integrated circuit 1 comprises internal logic 2 which may perform memory and/or core functions. The core functions may be performed by a microcontroller, microprocessor, digital signal processor, state machine, logic gates, or essentially any digital processing circuit. The integrated circuit has I/O pins 3 for connecting to other system components. In accordance with the IEEE 1149.1 standard, 4 or 5 of the I/O pins 3 are dedicated to the JTAG interface for control and input and output functions. The standard JTAG compliant I/O pins are test-clock (TCK), test mode select (TMS), optional test reset (TRST), test data input (TDI), and test data output (TDO).
At each non-JTAG I/O pin 3 there is a cell 4 to access the I/O pins 3 at an internal point within the integrated circuit. The cells 4 may be placed at other points within integrated circuit 1 in order to access desired points within the integrated circuit. The cells 4 are connected to form a register 5 which is the basis for the internal architecture. Register 5 is a shift-register chain formed by serially interconnecting the cells 4. Each cell 4 in the register 5 represents a desired access point within the integrated circuit 1. By connecting the individual cells 4 in series, the register 5 provides a serial path representing desired points within the integrated circuit 1. The serial path may be used for monitoring the desired points or inserting data at the desired points by shifting data into and out of register 5, respectively. Data may be shifted into or out of the register 5 through the serial path coupled to the TDI input and to the TDO output. By using the internal architecture described above, an external debugger is able to access locations within the integrated circuit through the JTAG interface. The external debugger is able to insert data into the integrated circuit and monitor data in the integrated circuit by serially shifting data into and out of register 5, respectively, through the JTAG interface. This is an improvement over accessing the integrated circuit through the external pins only, because, as discussed above, errors detected at the external pins can be caused by any number of internal components in the appropriate signal path to the external pin. The internal architecture reduces this problem by allowing internal points within the integrated circuit to be accessed at the internal points, thereby removing the chance that detected errors are the result of other components within the path between the internal points and the external pins.
During monitoring or inserting data, the cells 4 prevent the normal flow of data until the data is serially shifted in/out of shift-register 5. For example, during testing, data is prevented from flowing between pins 3 and internal logic 2. This arrangement disrupts the operation of integrated circuit 1 and prevents real-time debugging since the flow of data is interrupted during the monitoring and inserting of data into the shift-register 5.
The present invention discloses an integrated circuit comprising a debugger, memory, and core, in which the debugger, memory, and core are on a single integrated circuit. By integrating the debugger into the same integrated circuit as the memory and the core, the debugger may directly access points internal to the memory and the core. By directly accessing the memory and the core, improvements over prior art circuits can be achieved, such as real-time debugging, and faster and more accurate debugging.
The debugger comprises an instruction register for storing one or more debugging instructions, a status vector register for storing one or more status events, a comparator for comparing one or more status events with internal integrated circuit signals to generate an indicator at its output in the event of a match, a finite state machine (FSM), and a multiplexer controlled by the FSM for inserting debugging instructions from the instruction register into the integrated circuit for use by a core.
A method for debugging an integrated circuit with an integrated circuit debugger is also provided. The method for debugging an integrated circuit comprises the steps of specifying an event internal to an integrated circuit, detecting the event by internally monitoring the integrated circuit for the occurrence of the event, and performing debugging instructions upon the occurrence of the event.